Gigamax Technologies Technical Resources

New Postings!

Recent Developments in Jitter and Signal Integrity Measurement and Analysis at Multiple Gbps or GHz (DesignCon2007 Tech Forum - PowerPoint - 2.6 Mb pdf)

A Generic and Higher Order Model for High-Speed Test Interface Analysis and De-emedding (white paper - 450KB)

A Generic and Higher Order Model for High-Speed Test Interface Analysis and De-embedding (DesignCon2007 - PowerPoint - 430KB)

Challenges and Solutions for Signal Integrity and Jitter Testing for PCIe 2.0 @ 5GT/s (Devcon 2006 Power Point presentation - 2.5 Mb pdf)

New Phase Locked-Loop (PLL) Measurement and Analysis Methods (2nd - 3rd Order) Without a Stimulus (DesignCon 2006 Power Point Presentation - 1Mb pdf)

Characterization and Production Testing at 3.2 - 5.0 GB/s for PCI Express II and FB DIMM (SemiCon Japan 2005 presentation paper - 822 Kb)

Characterization and Production Testing at 3.2 - 5.0 GB/s for PCI Express II and FB DIMM (Power Point Presentation - 1.4 Mb)

Transfer Functions For The Reference Clock Jitter In A Serial Link: Theory And Applications (DesignCon 2005 presentation)
(Paper - PDF - 753Kb)

Transfer Functions For The Reference Clock Jitter In A Serial Link: Theory And Applications
(Presentation - PDF -407Kb)

Will "Heisenberg Uncertainty Principle" Hold For Designing and Testing Multiple GB/s ICs ?
(Paper - PDF - 111KB)

Will "Heisenberg Uncertainty Principle" Hold For Designing and Testing Multiple GB/s ICs ?
(Presentation - PDF - 137KB)

Statistical and System Transfer Function Based Method For Jitter and Noise Estimation In Communication Design and Test
(Paper - PDF - 63Kb)

Statistical and System Transfer Function Based Method For Jitter and Noise Estimation In Communication Design and Test
(Presentation - PDF- 331Kb)

Characterizing Jitter Histograms for Clock and DataCom Applications
(Paper - PDF-1.75Mb)

Characterizing Jitter Histograms for Clock and DataCom Applications
(Presentation - PDF-3.3Mb)

Paradigm Shift for Jitter and Noise in Design and Test
(Paper - PDF - 189Kb)

Paradigm Shift for Jitter and Noise in Design and Test
(Presentation - PDF-315Kb)

A Generic Test Path and DUT Model for DataCom ATE
(Paper - PDF-313Kb)

A Generic Test Path and DUT Model for DataCom ATE
(Presentation - PDF-316Kb)

Production Test Challenges and Possible Solutions for Multiple GB/s ICs
(Paper - PDF-64Kb)

Requirements, Challenges, and Solutions for Testing Multiple GB/s ICs in Production
(Paper - PDF-95Kb)

Requirements, Challenges, and Solutions for Testing Multiple GB/s ICs in Production
(Presentation - PDF-220Kb)

An Overview of Signal Integrity
(Paper - PDF-816Kb)

Impact of Various Source Jitter Components on Equalized Link Performance
(Paper - PDF-1.01Mb)

The Effect of Inserted ISI on Transition Density Plots and DCD & ISI Histograms of MJS Patterns
(Presentation - PDF-466Kb)

Simultaneously Measuring & Anlayzing PLL Transfer Function & Noise Process
(Presentation - PDF-276Kb)

Simultaneously Measuring & Anlayzing PLL Transfer Function & Noise Process
(Paper - PDF-540Kb)

Comparison & Correlation of Signal Integrity Measurement Techniques
(Presentation - PDF-1327Kb)

Comparison & Correlation of Signal Integrity Measurement Techniques
(Paper - PDF-1327Kb)

Intro to Jitter Analysis (PDF - 490Kb)

Applying Signal Analysis Theory to Clock and PLL Specifications
(PDF - 478Kb)

Signal Integrity: It Matters for Both Electrical and Optical Devices and Systems

Can Fibre Channel Jitter Standards Bring Harmony to a Tumultuous Network
(PDF - 558Kb)

Signal Integrity: How to Measure it Correctly (681Kb)